Method for performing processor resource allocation in an electronic device, and associated apparatus

ABSTRACT

A method for performing processor resource allocation in an electronic device is provided, where the method may include the steps of: obtaining task-related information to determine whether a task of a plurality of tasks is a heavy task (e.g. the heavy task may correspond to heavier loading than others of the plurality of tasks), to selectively utilize a specific processor core within a plurality of processor cores to perform the task, and determining whether at least one scenario task exists within others of the plurality of tasks, to selectively determine according to application requirements a minimum processor core count and a minimum operating frequency for performing the at least one scenario task; and performing processor resource allocation according to a power table and system loading, to perform any remaining portion of the plurality of tasks. An apparatus for performing processor resource allocation according to the above method is provided.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.62/166,252, which was filed on May 26, 2015, and is included herein byreference.

BACKGROUND

The present invention relates to processor control of an electronicdevice, particularly to a performance on demand processor resourceallocation method in an electronic device, and an associated apparatus.

According to the related art, as the progress of modern electronicdevices, the CPU topology changed dramatically and also the diversityincreased. For example, from symmetric multi-processor (SMP) toheterogeneous multi-processor (HMP), asymmetric multi-processor (AMP),and even hybrid architecture, developed for system flexibility, powerefficiency, thermal strategy, product differentiation, etc. Comparedwith SMP, these non-SMP topologies are typically composed of asymmetricCPUs variant on physical characteristics, including micro-architecture,computing capability, and power efficiency. These physical variancesbetween asymmetric non-SMP CPUs challenge traditional technologies ofSMP hot-plugging and dynamic voltage and frequency scaling (DVFS)dramatically.

Conventional hot-plugging and DVFS, originated from SMP systems, aredesigned to adjust the number of active cores and the associatedoperating frequencies according to the system loading. For example, ifthe system loading is higher than a certain threshold, one or more coresmay be plugged and frequency up-shifting may be performed. If the systemloading is lower than a certain threshold, one or more cores may beun-plugged and frequency down-shifting may be performed. But SMP systemswill not consider which cores to adjust, since all cores are notdifferentiated. On a non-SMP system, to balance between performance andlow-power, decision making of hot-plugging and DVFS may become morecomplex. In addition, on a HMP, a bigger core may have betterperformance with higher power cost, while a smaller one may have morebalanced power efficiency. According to physical characteristics, twosmall cores may provide the same computing capability as one big core,but with less total power consumption. However, a task is not alwaysdividable, and the performance of running on one of the two small coresmay be half of (or less than) that of the one big core. Therefore,performance and low-power balance may have become an important issue onmodern mobile devices, especially on an asymmetric system. For example,choosing a wrong class of CPU may result in terrible user experience orunnecessary system power waste. The disclosed implementation method andthe associated apparatus may be applied to one or a combination ofvarious types of processor resources, such as the SMP architecture thattypically has multiple cores with the same DMIPS (i.e. Dhrystone MillionInstructions Per Second (MIPS)) and operating frequency (e.g. in unit ofmegahertz (MHz)), the HMP architecture that typically has multiple coreswith different DMIPS and operating frequencies and different powerconsumption, and the AMP architecture that typically has multiple coreswith the same DMIPS, but different operating frequencies or differentmanufacturing processes.

FIG. 1 is a diagram of a conventional method in the related art. Forexample, the conventional method may comprise processor resources 110including a plurality of processor cores (e.g. central processing unit(CPU) cores), examples of which may comprise the processor coresCPU_(X), CPU_(Z), CPU_(Y), CPU_(L), and CPU_(T) shown around the uppermost of FIG. 1. A processor core depicted with dashed lines indicatesthat this processor core is hot-unplugged (e.g. the power thereof may betemporarily turned off). A processor core depicted with non-dashed linesindicates that this processor core is hot-plugged (e.g. the powerthereof may be temporarily turned on) and operated in its full orpartial capability, depends on the ratio of non-dashed lines compared todashed lines. The shaded content(s) depicted in a processor coreindicates the working load of this processor core compared to itscomputing capability. The statuses of the processor cores may vary fromtime to time.

According to the related art, the conventional method may operate legacyhot-plug/DVFS method. For example, in the first transition taking around10 milliseconds (ms) or more, the DVFS operation of the conventionalmethod may up shift the online CPU frequency to a reasonable level(which may be the maximum capability of the online CPU). In the secondtransition taking around 100 ms or more, when the existing online CPUscannot handle the overall system loading, the hot-plug operation of theconventional method may strategically enable CPU(s) to ease workloadtensions. The strategies of enabling CPUs may be the consideration ofmost powerful, most power efficient, most power saving, etc. However,the conventional method encounters some problems. For example, theconventional method may be late to response, the independent usage ofhot-plugging and DVFS may cause extra delay and response time.

As mentioned, there are some problems in the related art. Thus, a novelmethod is required to enhance the processor control of an electronicdevice.

SUMMARY

It is an objective of the claimed invention to provide a method forperforming processor resource allocation in an electronic device, and anassociated apparatus, in order to solve the above-mentioned problems.

According to at least one embodiment, a method for performing processorresource allocation in an electronic device is provided, where themethod may comprise the steps of: obtaining task-related information todetermine whether a task of a plurality of tasks is a heavy task (e.g.the heavy task may correspond to heavier loading than others of theplurality of tasks), to selectively utilize a specific processor corewithin a plurality of processor cores to perform the task, anddetermining whether at least one scenario task exists within others ofthe plurality of tasks, to selectively determine according toapplication requirements a minimum processor core count and a minimumoperating frequency for performing the at least one scenario task; andperforming processor resource allocation according to a power table andsystem loading, to perform any remaining portion of the plurality oftasks. According to some embodiments, an apparatus for performingprocessor resource allocation according to the above method is provided,where the apparatus may comprise at least one portion (e.g. a portion orall) of the electronic device.

According to at least one embodiment, an apparatus for performingprocessor resource allocation in an electronic device is provided, wherethe apparatus may comprise at least one portion (e.g. a portion or all)of the electronic device. For example, the apparatus may comprise aplurality of processor cores that may be positioned within theelectronic device, and may further comprise a control circuit that maybe embedded within the plurality of processor cores or positionedoutside the plurality of processor cores. The plurality of processorcores may be arranged for selectively performing operations for theelectronic device. In addition, the control circuit may be arranged forobtaining task-related information to determine whether a task of aplurality of tasks is a heavy task (e.g. the heavy task may correspondto heavier loading than others of the plurality of tasks), toselectively utilize a specific processor core within the plurality ofprocessor cores to perform the task, and determining whether at leastone scenario task exists within others of the plurality of tasks, toselectively determine according to application requirements a minimumprocessor core count and a minimum operating frequency for performingthe at least one scenario task. In addition, the control circuitperforms processor resource allocation according to a power table andsystem loading, to perform any remaining portion of the plurality oftasks.

It is an advantage of the present invention that, for a given set ofprocessor resources, such as the plurality of processor cores mentionedabove, the present invention method and the associated apparatus canallocate necessary processor cores based on performance requirementswith energy concerns. For example, by performing processor hot-plugging(e.g. central processing unit (CPU) hot-plugging or CPU corehot-plugging) and dynamic voltage and frequency scaling (DVFS), thepresent invention method and the associated apparatus may try to makethe best decision between clusters and CPUs with different physicalcharacteristics of computing capability and power efficiency, to fulfillperformance requirements for an energy efficient system. As both of userexperience and power saving are quite sensitive in milliseconds, thepresent invention method and the associated apparatus may performhot-plugging and DVFS in a susceptible manner to twinkle changeableperformance requirements and responses an appropriate adjustment withenergy concerns. In addition, the present invention method and theassociated apparatus can perform power control properly with fewer sideeffects. In comparison with the related art, the present inventionmethod and the associated apparatus can prevent, or greatly decrease theprobability of, improper core allocation and/or improper frequencyallocation. As a result, the best overall performance of an electronicdevice may be achieved.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the embodiments that are illustratedin the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a conventional method in the related art.

FIG. 2 is a diagram of an apparatus for performing processor resourceallocation in an electronic device according to an embodiment of thepresent invention.

FIG. 3 illustrates a flowchart of a method for performing processorresource allocation in an electronic device according to an embodimentof the present invention.

FIG. 4 illustrates a control scheme involved with the method shown inFIG. 3 according to an embodiment of the present invention.

FIG. 5 illustrates some implementation details of the control circuitshown in FIG. 2 according to an embodiment of the present invention.

FIG. 6 illustrates a timing chart involved with the method shown in FIG.3 according to an embodiment of the present invention.

DETAILED DESCRIPTION

Certain terms are used throughout the following description and claims,which refer to particular components. As one skilled in the art willappreciate, electronic equipment manufacturers may refer to a componentby different names. This document does not intend to distinguish betweencomponents that differ in name but not in function. In the followingdescription and in the claims, the terms “include” and “comprise” areused in an open-ended fashion, and thus should be interpreted to mean“include, but not limited to . . . ”. Also, the term “couple” isintended to mean either an indirect or direct electrical connection.Accordingly, if one device is coupled to another device, that connectionmay be through a direct electrical connection, or through an indirectelectrical connection via other devices and connections.

FIG. 2 is a diagram of an apparatus 100 for performing processorresource allocation in an electronic device according to an embodimentof the present invention, where the apparatus 100 may comprise at leastone portion of the electronic device. For example, the apparatus 100 maycomprise a portion of the electronic device mentioned above, and moreparticularly, can be at least one hardware circuit such as at least oneintegrated circuit (IC) within the electronic device and associatedcircuits thereof. In another example, the apparatus 100 can be the wholeof the electronic device mentioned above. In another example, theapparatus 100 may comprise a system comprising the electronic devicementioned above (e.g. a wireless communications system comprising theelectronic device). Examples of the electronic device may include, butnot limited to, a mobile phone (e.g. a multifunctional mobile phone), atablet, and a personal computer such as a laptop computer or a desktopcomputer.

According to this embodiment, the apparatus 100 may comprise theaforementioned processor resources 110 including a plurality ofprocessor cores, which may be positioned within the electronic device inthis embodiment. For example, the apparatus 100 may comprise at leastone processor in the electronic device, and the aforementioned at leastone processor may comprise the plurality of processor cores. For bettercomprehension, the processor cores CPU_(X), CPU_(Z), CPU_(Y), CPU_(L),and CPU_(T) are illustrated as examples of the plurality of processorcores of this embodiment. As shown in FIG. 2, the apparatus 100 mayfurther comprise a control circuit 120 that may be positioned outsidethe plurality of processor cores. According to some embodiments, thecontrol circuit 120 may be embedded within the plurality of processorcores. For example, the control circuit 120 may be implemented with theaforementioned at least one processor having at least one program modulerunning thereon, such as a kernel program module modified from anexisting kernel of an operating system (OS).

As shown in FIG. 2, the processor core CPU_(X) partially depicted withsolid lines indicates that the processor core CPU_(X) is online (whichmeans the processor core CPU_(X) may be hot-plugged, for example, thepower thereof may be temporarily turned on) and is operating not at amaximum operating frequency since the rest dashed line depicted theunused frequency capability, while the processor core CPU_(Y) completelydepicted with solid line indicates that the processor core CPU_(Y) isonline (which means the processor core CPU_(Y) may be hot-plugged, forexample, the power thereof may be temporarily turned on) and isoperating at a maximum operating frequency, where the cores CPU_(Z),CPU_(L), and CPU_(T) completely depicted with dashed lines indicate thatthe processor cores CPU_(Z), CPU_(L), and CPU_(T) are offline (whichmeans the processor cores CPU_(Z), CPU_(L), and CPU_(T) may behot-unplugged, for example, the power thereof may be temporarily turnedoff). Same radius with half total height depicted that the processorcores have same DMIPS, but the ratio of the maximum operating frequencyis 1:2, for example CPU_(X), CPU_(Y), and CPU_(Z) compare to CPU_(L).And greater radius indicates that the processor core has higher DMIP. Asthe height of the processor core CPU_(T) is greater than that of theprocessor cores CPU_(X), CPU_(Y), and CPU_(Z), the maximum operatingfrequency of the processor core CPU_(T) is higher than that of theprocessor cores CPU_(X), CPU_(Y), and CPU_(Z). The statuses of any ofthe plurality of processor cores, such as that of any of the processorcores CPU_(X), CPU_(Z), CPU_(Y), CPU_(L), and CPU_(T) shown in FIG. 2,may vary from time to time.

As any of the plurality of processor cores may be temporarilyhot-plugged or hot-unplugged, the plurality of processor cores may bearranged for selectively performing operations for the electronicdevice. In addition, the control circuit 120 may be arranged forclassifying the plurality of tasks into a plurality of categories, andfurther assigning or re-assigning one or more tasks to one or more ofthe plurality of processor cores according to whether the aforementionedone or more tasks belong to which of the plurality of categories.According to this embodiment, the control scheme may be utilized forfulfilling performance requirement with energy efficient concerns,applicable for any modern CPU topology, including but not limited toSMP, HMP, AMP, and hybrid architecture. Besides system overall loading,the control scheme may take into consideration the computing requirementvarying task by task, which should be treated individually and not tomingle with the concept of system loading. For example, the controlscheme categorizes performance-concerned tasks by characteristics,including but not limited to tasks for frame rendering and tasks withheavy loading, to allocate desired number of cores and correspondingclass or frequency. Based on performance demanded number of cores,class, frequency, and overall system loading, the control scheme refersto a power table for minimum power consumption, which satisfiessystem-wide requirements. As a result, the apparatus 100 of thisembodiment may resolve the above problems of the conventional methodshown in FIG. 1.

According to some embodiments, for a given set of CPU resources, theapparatus 100 operating according to the control scheme may allocatenecessary CPUs based on performance requirements and energy concerns.For example, by utilizing CPU hot-plugging and DVFS, the apparatus maytry to make the best decision between cluster(s) and CPU(s) withdifferent physical characteristics of computing capability and powerefficiency to fulfill performance requirements.

FIG. 3 illustrates a flowchart of a method 200 for performing processorresource allocation in an electronic device according to an embodimentof the present invention. The method 200 shown in FIG. 3 can be appliedto the apparatus 100 shown in FIG. 2 and the aforementioned at least oneprocessor thereof, and can be applied to the control circuit 120mentioned above, no matter whether the control circuit 120 is positionedoutside the plurality of processor cores of the embodiment shown in FIG.2 or embedded within the plurality of processor cores of someembodiments described above.

In Step 210, the control circuit 120 may obtain task-related informationto determine whether a task of a plurality of tasks is a heavy task,then selectively utilize a specific processor core within a plurality ofprocessor cores to perform the task, where the specific processor coremay be a processor core having higher computing capability than othersof the plurality of processor cores, in order to satisfy the requirementof the heavy task. For example, when the task is the heavy task, thecontrol circuit 120 may utilize the specific processor core (e.g. theprocessor core having higher computing capability than the others of theplurality of processor cores and satisfying the requirement of the heavytask) to perform the task. In order to achieve the best performance, thespecific processor core may operate at the highest operating frequencythereof, such as the maximum operating frequency available for thespecific processor core. According to some embodiments, the task-relatedinformation may be obtained from a program module running on theelectronic device, such as the kernel program.

For example, the task-related information may comprise a queue time,which represents a time period that the task is in the queue, and mayfurther comprise a successive execution time, which represents a timeperiod that the task is executed right after the queue. The controlcircuit 120 may determine whether the summation of the queue time andthe execution time satisfies a predetermined criterion (e.g. this mayindicate that the heavy task corresponds to heavier loading than othersof the plurality of tasks), to determine whether the task is the heavytask. For example, when the summation of the queue time and theexecution time reaches a predetermined time threshold, the controlcircuit 120 may determine that the task is the heavy task. In anotherexample, when the ratio of the summation of the queue time and theexecution time to a certain time period reaches a predetermined ratiothreshold, the control circuit 120 may determine that the task is theheavy task.

In Step 220, the control circuit 120 may determine whether at least onescenario task exists within others of the plurality of tasks, toselectively determine according to application requirements a minimumprocessor core count and a minimum operating frequency for performingthe aforementioned at least one scenario task. For example, when theaforementioned at least one scenario task exists, the control circuit120 may determine according to the application requirements for theminimum processor core count and the minimum operating frequency forperforming the aforementioned at least one scenario task. Moreparticularly, when the aforementioned at least one scenario task exists,the control circuit 120 may utilize at least one other processor corewithin the others of the plurality of processor cores to perform theaforementioned at least one scenario task, where the number of theaforementioned at least one other processor core is greater than orequal to the minimum processor core count, and the operating frequencyof the aforementioned at least one other processor core is greater thanor equal to the minimum operating frequency required by the applicationfor the scenario task.

In Step 230, the control circuit 120 may perform processor resourceallocation according to the power table and system loading, to performany remaining portion of the plurality of tasks, such as the othertask(s) within the plurality of tasks. For example, the control circuit120 may sum up a workload of all remaining tasks and then perform tablelookup operation(s) according to the power table, to adjust the numberof processor cores and share the overall workload, where the chosenprocessor core(s) corresponding to the least power consumption may havethe highest priority to be utilized in Step 230.

In some embodiments, the control circuit 120 may take into considerationthe power table and the overall workload, to select the best-fittedallocation, which fulfills the system requirement with the lowest powercost. For example, the system loading in these embodiments may be anumber to represent overall workload, while diverse task characteristicsmay not be considered.

According to some embodiments, the control circuit 120 may performloading measurement on the task to generate a loading measurementresult. Examples of the loading measurement result may include, but notlimited to, the queue time, the execution time, and a derivative of bothof the queue time and the execution time (e.g. the summation of thequeue time and the execution time, or the ratio of the summation of thequeue time and the execution time to the certain time period). Inaddition, the control circuit 120 may generate the task-relatedinformation mentioned in Step 210 according to the loading measurementresult. For example, in Step 210, when the loading measurement resultreaches a predetermined threshold (e.g. the predetermined time thresholdor the predetermined ratio threshold, based on different examples of thepredetermined criterion), the control circuit 120 may determine that thetask of the plurality of tasks is the heavy task. For betterillustration, the loading measurement result may vary within the rangefrom 0% through to 100%, and the predetermined threshold may be definedas 90% or another fixed value, based on various requirements. This isfor illustrative purposes only, and is not meant to be a limitation ofthe present invention.

According to some embodiments, such as one or more of the embodimentsshown in FIGS. 4-7, the control circuit 120 may categorize the pluralityof tasks into the plurality of categories, where the plurality ofcategories may comprise a “heavy task category”, a “scenario category”,and an “others category”.

TABLE 1 Category Heavy task Scenario Others Number of tasks N_(HT)N_(SCE) N_(OTH) Accumulated loading AccLoad_(HT) AccLoad_(SCE)AccLoad_(OTH) Most Cores N_(HT) powerful Frequency F_(MAX) CPUSystem-wide Cores N_(SCE) ↑ CPU Frequency F_(SCE) ↑

For example, the control circuit 120 may classify the plurality of tasksinto the plurality of categories by characteristics of the tasks, suchas the categories listed in Table 1. Examples of the plurality ofcategories may include, but not limited to, the heavy task category(labeled “Heavy task” in Table 1), the scenario category (labeled“Scenario” in Table 1), and the aforementioned others category (labeled“Others” in Table 1). The heavy task category may correspond to theheavy task mentioned in Step 210, the scenario category may correspondto the at least one scenario task mentioned in Step 220, and the otherscategory may correspond to the remaining portion of the plurality oftasks (i.e. the remaining portion mentioned in Step 230). For example,the at least one scenario task mentioned in Step 220 may comprise atleast one frame rendering task. For better comprehension, the framerendering task can be taken as an example of the scenario category,where a number N_(FPS) of tasks corresponding to the frame renderingtask, an accumulated loading parameter AccLoad_(FPS), and apredetermined operating frequency F_(FPS) can be taken as an example ofthe number N_(SCE) of tasks corresponding to the scenario category, theaccumulated loading parameter AccLoad_(SCE), and the predeterminedoperating frequency F_(SCE), respectively.

Regarding the scenario category, suppose that the apparatus 100 isupdating a frame by performing one or more tasks corresponding to framerendering. The control circuit 120 may determine some parametersassociated with the scenario category, such as a set of frame per second(FPS) parameters. For example, there may be N_(FPS) frame renderingtasks, where the number N_(FPS) is an integer greater than or equal tozero. Examples of the set of FPS parameters may include (but not limitedto):

(F0). The accumulated loading parameter AccLoad_(FPS), i.e. theaccumulated loading corresponding to frame rendering task(s);(F1). The minimum number of online cores that are required for framerendering task(s) within the plurality of processor cores, such as anumber that is equal to N_(FPS); and(F2). The minimum frequency required for these online cores, such as thepredetermined operating frequency F_(FPS).To satisfy the requirements of frame rendering task(s), the number ofonline cores that are required for frame rendering task(s) within theplurality of processor cores can be equal to or greater than N_(FPS),and the operating frequency of each processor cores applied to the framerendering tasks may be equal to or greater than F_(FPS).

Regarding the heavy task category, the control circuit 120 may determinesome parameters associated to the heavy task category. For example,there may be N_(HT) heavy loading tasks within the plurality of tasksmentioned in Step 210, where the number N_(HT), is an integer greaterthan or equal to zero. Examples of the set of heavy task (HT) parametersmay include (but not limited to):

(H0). The accumulated loading parameter AccLoad_(HT), i.e. theaccumulated loading corresponding to heavy task(s); and(H1). The number of most powerful processor cores (e.g. most powerfulCPU cores) that are required for heavy task(s) within the plurality ofprocessor cores, such as a number that is equal to N_(HT). According tosome embodiments, when the power is sufficient and there is no need tosave power, the number of most powerful processor cores that arerequired for heavy task(s) within the plurality of processor cores canbe a number that is greater than or equal to N_(HT). According to someembodiments, each processor core of the plurality of processor cores maybe the processor core of a single core processor, and therefore the setof HT parameters may include the number of most powerful processors inthese embodiments.

Regarding the others category, for example, suppose there are N_(OTH)other tasks, where the number N_(OTH), i.e. the task count of theaforementioned other tasks, is an integer greater than or equal to zero.The control circuit 120 may determine some parameters associated to theothers category, such as the accumulated loading parameterAccLoad_(OTH), i.e. the accumulated loading corresponding to othertask(s).

FIG. 4 illustrates a control scheme involved with the method 200 shownin FIG. 3 according to an embodiment of the present invention. Accordingto the task count N_(HT) of the heavy tasks, the control circuit 120 maydetermine the number of most powerful processor cores (e.g. mostpowerful CPU cores) to be a proper value for efficiently completing theN_(HT) heavy tasks. And each most powerful processor core may be workingat the maximum operating frequency available F_(MAX). As shown in FIG.4, the height and radius indicates that the processor core CPU_(T) isthe most powerful processor cores.

The plurality of tasks may comprise a set of frame rendering tasks P₁,P₂, and P₃, a heavy task P₄, and one or more other tasks P_(N). Thecontrol circuit 120 may assign the processor core CPU_(T) to perform theheavy task P₄, with the processor core CPU_(T) working at least at aminimum operating frequency required by the heavy task P₄, In addition,with aid of the power table 20, the control circuit 120 may assign theprocessor cores CPU_(X), CPU_(Z), and CPU_(Y) to perform the set offrame rendering tasks P₁, P_(Z), and P₃, respectively. Additionally, thecontrol circuit 120 may assign the processor core CPU_(L) together withpart of capability of the processor cores CPU_(X), CPU_(Z), and CPU_(Y)to perform the aforementioned one or more other tasks P_(N). In general,when allocating processing resource for one or more other tasks P_(N),the control circuit 120 may refer to the power table 20 forconfigurations corresponding to the minimum power consumption. Theprinciple of the method typically satisfies the following requirements:

(R1). At least N_(HT) most powerful processor cores online, each ofwhich working at the maximum operating frequency available F_(MAX) forthese most powerful processor cores;(R2). Besides heavy tasks, the apparatus 100 handles accumulated loadingof scenario tasks or tasks from apps. With at least N_(SCE) processorcores being online, each of which working at a required operatingfrequency, such as the predetermined operating frequency F_(SCE) orabove; and(R3). Base on power efficiency concerns, use power table to allocateprocessor cores for one or more other tasks.

In the N_(SCE) processor cores in the requirement R2, the N_(HT) mostpowerful processor cores may be excluded, which means the N_(HT) mostpowerful processor cores are not within the group of N_(SCE) processorcores. In addition, with the above requirement R1 being satisfied, inStep 210, when the task is the heavy task, the control circuit 120 mayutilize a set of specific processor cores within the plurality ofprocessor cores, such as the N_(HT) most powerful processor cores, toperform the task mentioned in Step 210, where the set of specificprocessor cores comprises the specific processor core. For example, eachof the set of specific processor cores may operate at the highestoperating frequency thereof, such as the maximum operating frequencyavailable F_(MAX). Typically, the set of specific processor cores maycorrespond to the highest computing capability with respect to theplurality of processor cores, and the set of specific processor cores(such as the N_(HT) most powerful processor cores) can be utilized forcompleting the heavy task as soon as possible. In some embodiments, whenthe task mentioned in Step 210 is the heavy task, the control circuit120 may utilize the set of specific processor cores within the pluralityof processor cores to perform a set of heavy tasks (which may comprisethe task mentioned in Step 210) such as the N_(HT) heavy tasks,respectively. For example, each of the set of specific processor coresmay operate at the highest operating frequency thereof, such as themaximum operating frequency available F_(MAX).

FIG. 5 illustrates some implementation details of the control circuit120 shown in FIG. 2 according to an embodiment of the present invention,where the control circuit 120 may be implemented with the aforementionedat least one processor having a plurality of program modules runningthereon. For example, the plurality of program modules may comprise aLinux kernel program module (labeled “LINUX KERNEL” in FIG. 5, forbrevity), a library program module (labeled “LIBRARIES” in FIG. 5, forbrevity), and a processor resource allocation (PRA) program module(labeled “PRA” in FIG. 5, for brevity). Please note that the Linuxkernel program module can be taken as an example of the aforementionedkernel program module modified from the existing kernel of the OS in theembodiment shown in FIG. 2. In addition, the Linux kernel program modulemay comprise some sub-modules such as a scheduler and a CPU topologyunit (labeled “CPU Topology” in FIG. 5, for brevity), and the libraryprogram module may comprise some sub-modules such as the power table(e.g. the power table 20) and FIG. 5 an i-boost unit (labeled “iBoost”in FIG. 5, for brevity).

As shown in FIG. 5, the processor resource allocation program module mayobtain contents of the power table from the library program module, andmay obtain the number N_(SCE), i.e. the task count of the aforementionedscenario tasks, and the predetermined operating frequency F_(SCE) fromthe i-boost unit imbedded within the performance service unit of thelibrary program module. As the Linux kernel program module may determinesome parameters that are further needed for performing processorresource allocation operations, the processor resource allocationprogram module may obtain these parameters from the Linux kernel programmodule and perform the processor resource allocation operationsaccording to these parameters. For example, the scheduler of the Linuxkernel program module may determine the number N_(HT) (i.e. the taskcount of the aforementioned N_(HT) heavy tasks), the accumulated loadingparameter AccLoad_(FPS) (i.e. the accumulated loading corresponding toframe rendering task(s)), the accumulated loading parameterAccLoad_(OTH) (i.e. the accumulated loading corresponding to othertask(s)), and the system TLP. For example, in Step 230, the controlcircuit 120 may check the system TLP, to determine whether Step 210should be re-entered, and in a situation where Step 210 is re-entered,re-performing some operations regarding processor resource allocation(e.g. the operations of the working flow starting from Step 210) may berequired. This is for illustrative purposes only, and is not meant to bea limitation of the present invention. In addition, the CPU topologyunit may determine information regarding topology and efficiency, suchas CPU topology information and CPU efficiency information. As a result,the processor resource allocation program module may perform theprocessor resource allocation operations according to the parameters andthe power table that are obtained from the Linux kernel program moduleand according to the other parameters obtained from the library programmodule, to dynamically determine a plurality of processor resourceallocation control parameters. For example, the plurality of processorresource allocation control parameters may comprise the number of coresfor each class (more particularly, each category of the plurality ofcategories), such as the number of most powerful processor cores for theheavy task category (e.g. a number that is equal to N_(HT)) and theminimum number of online cores that are required for frame renderingtask(s) for the scenario task category (e.g. a number that is greaterthan or equal to N_(SCE)). In addition, the plurality of processorresource allocation control parameters may further comprise thecorresponding frequency of each processor core concerned (labeled“corresponding frequency of each CPU” in FIG. 6, for bettercomprehension), such as the maximum operating frequency availableregarding the most powerful processor cores for the heavy task category(e.g. F_(MAX)) and the minimum frequency required for these online cores(e.g. the predetermined operating frequency F_(SCE)). According to someembodiments, examples of the corresponding frequency of each processorcore concerned may further comprise the aforementioned otherpredetermined operating frequency that is greater than the predeterminedoperating frequency F_(SCE), i.e. the other predetermined operatingfrequency determined for the processor core(s) having lower DMIPS in theembodiment shown in FIG. 5. For brevity, similar descriptions for thisembodiment are not repeated in detail here.

According to some embodiments, when one or more of the number N_(SCE)(i.e. the task count of the aforementioned scenario tasks), the minimumfrequency required for these online cores (e.g. the predeterminedoperating frequency F_(SCE)), and the number N_(HT) (i.e. the task countof the aforementioned N_(HT) heavy tasks) are varied, the processorresource allocation program module may re-perform the processor resourceallocation operations according to the latest parameters and the powertable, to update the plurality of processor resource allocation controlparameters. For brevity, similar descriptions for this embodiment arenot repeated in detail here.

FIG. 6 illustrates a timing chart involved with the method 200 shown inFIG. 3 according to an embodiment of the present invention. According tothis embodiment, during performing the processor resource allocationoperations, the control circuit 120 (more particularly, the processorresource allocation program module) not only controls the processorresources 110 in response to the tasks with heavy loading and the tasksfor frame rendering, but also cares the system TLP.

For example, the schedule tick shown in FIG. 6 may be a Linux-definedtime period for checking (e.g. ten milliseconds, or anotherpredetermined length of time), and the curves shown in FIG. 6, startingfrom the top to the bottom, can be referred to as the first curvethrough to the eighth curve in this embodiment. As shown in FIG. 6, acurve that is depicted with bold lines, such as the first curve (i.e.the uppermost curve), may indicate that a corresponding task is runningduring the schedule tick shown in FIG. 6. Similarly, a partial curvethat is depicted with bold line(s), such as a right portion of thesecond curve, may indicate that a corresponding task is running during asmaller length of time in which the bold line(s) are illustrated, whilea partial curve that is depicted with non-bold line(s), such as a leftportion of the second curve, may indicate that the corresponding task isnon-wakened (which may be regarded as “sleeping” in some embodiment, forbetter comprehension) during the time in which the non-bold line(s) areillustrated, where a shaded portion of a curve, such as a the shadedportion of the second curve, may indicate that the corresponding task iswakened but no processor core is assigned to perform this task duringthe time in which the shaded portion is illustrated.

In the real world, the system TLP typically alters in every moment whilethe apparatus 100 is scheduling enqueues and dequeues, whose behaviormay be too frequent for the apparatus 100 to react for each change. Ageneral compromised implementation may be sample-based tracking. Inaddition, when trying to increase CPU resources by referring to thesystem TLP, a sample-based method may bring some issues. For example,the most serious one is that a transient state may be sampled, andtherefore a false alarm may occur. Considering a task that is just wakenup before sampling at a sampling time point, the system TLP willincrease at this sampling time point, but the apparatus 100 may give uprunning this task at the next millisecond.

According to this embodiment, a “runnable duration” TLP may beintroduced to be utilized as the system TLP, to reflect whether the CPUresources are or are not sufficient. For example, under control of thecontrol circuit 120 (more particularly, the processor resourceallocation program module), except for heavy and frame rendering tasks,any task that satisfies the following formula may trigger the processorresource allocation program to re-allocate CPU resources:

((T _(RUNNABLE) *N _(ONLINE) _(_) _(CPU))/T _(ACC) _(_) _(ONLINE) _(_)_(CPU))>X%;

where the notation “T_(RUNNABLE)” may represent the runnable time (e.g.the time during which there is no processor core for running this task),the notation “N_(ONLINE) _(_) _(CPU)” may represent the number of onlineprocessor cores, the notation “T_(ACC) _(_) _(ONLINE) _(_) _(CPU)” mayrepresent the system-wide accumulated time of online processor cores,and the notation “X %” may represent a predetermined threshold such as apredetermined percentage. The predetermined percentage (i.e. X %) can betaken as an example of the predetermined ratio threshold. For brevity,similar descriptions for this embodiment are not repeated in detailhere.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A method for performing processor resourceallocation in an electronic device, the method comprising the steps of:obtaining task-related information to determine whether a task of aplurality of tasks is a heavy task, to selectively utilize a specificprocessor core within a plurality of processor cores to perform thetask; determining whether at least one scenario task exists withinothers of the plurality of tasks, and determining according toapplication requirements a minimum processor core count and a minimumoperating frequency for performing the at least one scenario task; andperforming processor resource allocation according to a power table andsystem loading, to perform any remaining portion of the plurality oftasks.
 2. The method of claim 1, wherein the step of determiningaccording to the application requirements the minimum processor corecount and the minimum operating frequency for performing the at leastone scenario task further comprises: when the at least one scenario taskexists, utilizing at least one other processor core within others of theplurality of processor cores to perform the at least one scenario task,wherein a number of the at least one other processor core is greaterthan or equal to the minimum processor core count and an operatingfrequency of the at least one other processor core is greater than orequal to the minimum operating frequency.
 3. The method of claim 1,wherein the step of obtaining the task-related information to determinewhether the task of the plurality of tasks is the heavy task toselectively utilize the specific processor core within the plurality ofprocessor cores to perform the task further comprises: when the task isthe heavy task, utilizing the specific processor core to perform thetask.
 4. The method of claim 3, wherein the step of obtaining thetask-related information to determine whether the task of the pluralityof tasks is the heavy task to selectively utilize the specific processorcore within the plurality of processor cores to perform the task furthercomprises: when the task is the heavy task, utilizing the specificprocessor core to perform the task with the specific processor coreoperating at a highest operating frequency thereof.
 5. The method ofclaim 1, further comprising: performing loading measurement on the taskto generate a loading measurement result; and generating thetask-related information according to the loading measurement result. 6.The method of claim 5, wherein the step of obtaining the task-relatedinformation to determine whether the task of the plurality of tasks isthe heavy task to selectively utilize the specific processor core withinthe plurality of processor cores to perform the task further comprises:when the loading measurement result reaches a predetermined threshold,determining that the task of the plurality of tasks is the heavy task.7. The method of claim 1, wherein step of obtaining the task-relatedinformation to determine whether the task of the plurality of tasks isthe heavy task to selectively utilize the specific processor core withinthe plurality of processor cores to perform the task further comprises:when the task is the heavy task, utilizing a set of specific processorcores within the plurality of processor cores to perform a set of heavytasks, respectively, the set of specific processor cores correspondingto highest computing capability with respect to the plurality ofprocessor cores.
 8. The method of claim 1, wherein the task-relatedinformation is obtained from a program module running on the electronicdevice.
 9. The method of claim 1, wherein the method is applied to atleast one processor in the electronic device, and the at least oneprocessor comprises the plurality of processor cores.
 10. An apparatusfor performing processor resource allocation in an electronic device,the apparatus comprising at least one portion of the electronic device,the apparatus comprising: a plurality of processor cores, positionedwithin the electronic device, arranged for selectively performingoperations for the electronic device; and a control circuit, embeddedwithin the plurality of processor cores or positioned outside theplurality of processor cores, arranged for obtaining task-relatedinformation to determine whether a task of a plurality of tasks is aheavy task, to selectively utilize a specific processor core within theplurality of processor cores to perform the task, and determiningwhether at least one scenario task exists within others of the pluralityof tasks, to selectively determine according to application requirementsa minimum processor core count and a minimum operating frequency forperforming the at least one scenario task, wherein the control circuitperforms processor resource allocation according to a power table andsystem loading, to perform any remaining portion of the plurality oftasks.
 11. The apparatus of claim 10, wherein when the at least onescenario task exists, the control circuit utilizes at least one otherprocessor core within others of the plurality of processor cores toperform the at least one scenario task, wherein a number of the at leastone other processor core is greater than or equal to the minimumprocessor core count and an operating frequency of the at least oneother processor core is greater than or equal to the minimum operatingfrequency.
 12. The apparatus of claim 10, wherein when the task is theheavy task, the control circuit utilizes the specific processor core toperform the task.
 13. The apparatus of claim 12, wherein when the taskis the heavy task, the control circuit utilizes the specific processorcore to perform the task with the specific processor core operating at ahighest operating frequency thereof.
 14. The apparatus of claim 10,wherein the control circuit performs loading measurement on the task togenerate a loading measurement result, and generates the task-relatedinformation according to the loading measurement result.
 15. Theapparatus of claim 14, wherein when the loading measurement resultreaches a predetermined threshold, the control circuit determines thatthe task of the plurality of tasks is the heavy task.
 16. The apparatusof claim 10, wherein when the task is the heavy task, the controlcircuit utilizes a set of specific processor cores within the pluralityof processor cores to perform a set of heavy tasks, respectively, theset of specific processor cores corresponding to highest computingcapability with respect to the plurality of processor cores.
 17. Theapparatus of claim 10, wherein the task-related information is obtainedfrom a program module running on the electronic device.
 18. Theapparatus of claim 10, wherein the apparatus comprises at least oneprocessor in the electronic device, and the at least one processorcomprises the plurality of processor cores.
 19. The apparatus of claim18, wherein the control circuit is implemented with the at least oneprocessor having at least one program module running thereon.